1. Field of the Invention
The present invention generally relates to the design and fabrication of integrated circuits, and more particularly, to electromigration verification in the design and fabrication of integrated circuits.
2. Description of the Related Art
Electromigration refers to the transport of mass in metals when stressed to high current densities. Electromigration occurs during passage of currents through thin metal conductors in integrated circuits. These thin metal conductors normally have sub-micron widths. Hence, metal piles up in some regions of the thin metal conductors and forms voids in other regions. The formation of voids in the thin metal conductors is very serious because such voids cause opens in the metal conductors which in turn cause the integrated circuit to fail. The pilling up or accumulation of metal in the thin metal conductors can also cause shorts between adjacent metal conductors which can also lead to circuit failure.
Electromigration sets a fundamental limit on the dimensions of conductors which carry current. The fundamental limit depends strongly on the choice of conductive material and its particular properties. Thus, the dimensions (e.g., width and height of the conductors) must be of a certain size to prevent, or at least minimize, failures due to electromigration for a particular fabrication process.
Conventionally, when preparing to fabricate an integrated circuit, process rules for a fabrication setup are used to specify the minimal dimensions and spacing that the conductors should have for the fabrication processing. The process rules are minimum values that are allowable to ensure proper fabrication of the integrated circuit. With respect to electromigration, the process rules pertain to dimensions or sizes of wires, contacts or other conductive features of the integrated circuit for different expected currents. If the circuit design satisfies the pertinent process rules, then failures due to electromigration are avoided or at least minimized.
Hence, before fabricating an integrated circuit, it is important to check that the circuit design does not violate the pertinent process rules. Although such checks could be done manually, manual checking is not practical because it is tedious, time consuming and susceptible to error. Chip assembly is an iterative process in which each step could require an EM check involving thousands of nets.
The conductors of the circuit design can carry either power or signals within the integrated circuit. Power lines tend to be in known locations with known current loads because a detailed analysis is usually performed when forming the power network. In contrast, signal lines tend to be plentiful and have complex routing and varying locations throughout the integrated circuit. Therefore, the checking of a circuit design for electromigration violations in signal lines is substantially more complex than for power lines. Here, even if manual checking were to be done on the signal lines (though often it is not), the checking would be incomplete, susceptible to error, and otherwise unacceptable. If manual checking fails to find one or more electromigration violations, the integrated circuits being fabricated would still fail and would have to be discarded or undergo revisions to the metal layers, both of which are costly.
At least one automated tool exists for checking power lines of an integrated circuit design against process rules for electromigration violations. PowerMill.TM. by Epic Design Technology, Inc. of Santa Clara, Calif. is such a product. However, since power lines tend to be in known locations with known current loads, the checking with respect to power lines can be accomplished. Nevertheless, the automated tool is unable to check signal lines against process rules for electromigration violations.
Thus, there is a need for an automated technique that is able to determine whether electromigration limits for a fabrication process are violated by signal lines within an integrated circuit design. To this end, related U.S. Pat. No. 5,831,867 filed Jun. 24, 1996, and entitled "METHOD AND SYSTEM FOR AUTOMATED ELECTROMIGRATION VERIFICATION", the entirety of which is incorporated herein by reference, describes an automated method and system for detecting electromigration violations in signal lines of an integrated circuit design to be fabricated. This computerized system and method are generally characterized by first identifying the driving nodes within the integrated circuit design, and then determining the drive strength of each driving node and a capacitance for each of the networks coupled to the driving nodes. Then, minimum dimensions of conductive signal traces of the integrated circuit design are determined by applying the drive strengths and capacitances to electromigration process rules. These minimum dimensions are compared with design dimensions to identify violations of the electromigration process rules in the integrated circuit design.
This system and method, while useful and far superior to manual techniques, nevertheless does suffer some drawbacks. One such drawback resides in the fact that the whole layout data base is taken as flat. That is, all functional boundaries are removed and net information is collected from the whole layout assuming the designer can see the entire chip layout. This technique treats all nets equally, regardless of their location or function within the chip layout. This in turn creates two distinct disadvantages. First, it is not possible to run the electromigration check until after design of the entire layout is completed. Second, due to the enormous number of nets found in a chip design, the processing time for checking the entire layout is prohibitively long. Typically, there may be on the order of five-hundred thousand or more nets on a single chip layout. The processing time needed to check for electromigration errors is so long as to discourage use of the tool each time a design variation is made to the chip layout.